Modern systems-on-chip (SoCs) are often designed with heterogeneous processing units that are selected for their different system characteristics. Typically, a processing unit, or agent, implements a cache for storing a local copy of data, and that agent assumes a particular coherence model, which defines a set of cache states and a set of coherent transactions that effect transitions between cache states. A coherence model enforces data coherence among agents that share the same coherence model.
However, different processing units, delivered as intellectual property blocks from different vendors, may implement different and incompatible coherence models, making integration of those processing units in a SoC difficult if not impossible. As a result, a SoC designer is faced with either higher design costs and longer development cycles or selection of compatible, but less optimal, processing units.